Improving Standard-Cell Design Flow using Factored Form Optimization

Published in Design Automation Conference (DAC), 2023

Factored form is a multi-level representation of a Boolean function that readily maps into CMOS technology. In particular, the number of literals of a factored form correlates well with the number of transistors. This paper focuses on developing techniques for minimizing the total factored form literals count in an and-inverter graph.

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