CV
Education
- Doctor of Philosophy - Ph.D. in Computer Science, EPFL (École Polytechnique Fédérale de Lausanne), 2020 - present
- M.Sc. in Computer Engineering, Télécom Paris, 2020
- Specilization in Smart Objects
- Thesis: Implementation of Algorithms for Synthesis of Digital Circuits
- M.Sc. in Computer Engineering, Politecnico di Torino, 2020
- Specilization in Embedded Systems
- Thesis: Implementation of Algorithms for Synthesis of Digital Circuits
- B.Sc. in Computer Engineering, Politecnico di Torino, 2017
Work experience
- Since 2020: Researcher and Ph.D. student at EPFL
- Research in electronics design automation (EDA), logic synthesis, and emerging technologies
- Teaching undergraduate and graduate courses and supervising Master’s projects
- Supervisor: Prof.Dr. Giovanni De Micheli, Integrated Systems Laboratory (LSI)
- 2022: Ph.D. Residency at X, the moonshot factory
- Logic synthesis and electronics design automation (EDA)
- Part of the work will be published at DAC 2023
- 2020: R&D Engineer at Télécom Paris
- Implementation of a model-checker for embedded system models on TTool
- The work has been published at MODELSWARD 21, MODELSWARD 22, and in a Springer book chapter
- Best poster award at MODELSWARD 21
- 2019: R&D Intern at Synopsys
- Implementation of timing-driven algorithms for synthesis of digital circuits
- The work is contained in the thesis Implementation of Algorithms for Synthesis of Digital Circuits
- Since 2017: Teaching Assistant
- At Politecnico di Torino: Algorithms and Programming in C, Object-oriented Programming
- At EPFL: Design Technologies for Integrated Systems, Real-time Embedded Systems, Digital Systems Design
Projects
- Mockturtle: A logic synthesis framework
- Development of logic synthesis algorithms in C++-17
- Available on GitHub
- TTool: A toolkit for edition, simulation and formal verification of UML and SysML diagrams
- Development of the SysML model-checker for formal verification (AVATAR)
- Available on GitLab
- LDPC HW Decoder: Design of a Low Density Parity Check codes channel decoder for 5G wireless communications
- Analysis and testing of different algorithms of low density parity check decoding followed by an efficient fixed-point hardware implementation for FPGA’s
- More on GitHub
Honors and Awards
- Best paper award at VLSI-SoC 2023: “Synthesis of SFQ Circuits with Compound Gates”
- First place in the IWLS 2022 contest: “Synthesis of small circuits for completely-specified multi-output Boolean functions represented using truth tables”
- Best Student Paper Candidate at IWLS 2021: “From Logic to Gates: A Versatile Mapping Approach to Restructure Logic”
- Best Poster Award at MODELSWARD 2021: “Direct Model-checking of SysML Models”
- EDIC IC Fellowship, EPFL, 2020
Publications
Talks
From Logic to Gates: A Versatile Mapping Approach to Restructure Logic
Talk at IWLS 2021,
Improving Standard Cell Design Flow using Factored Form Optimization
Talk at DAC 2023, San Francisco, California, USA
Technology Mapping Using Multi-output Library Cells
Talk at ICCAD 2023, San Francisco, California, USA
Teaching
Skills
- Languages
- English
- Italian
- French
- Programming
- C/C++
- VHDL, Verilog
- Java
- Python
- Many more
- Knowledge
- Algorithms
- Data structures
- Digital Design
- Microelectronics
- Computer Architectures
- Logic synthesis and optimization algorithms
- Satisfiability solving
Service and leadership
- Reviewer of several conferences and journals
- TCAD
- ICCAD
- DAC
- DATE
- IWLS
- DDECS
- Maintainer of the EPFL Combinational Benchmark Suite
- Track the best results and advances in logic synthesis
- Present annually at the International Workshop on Logic & Synthesis the new updates and best results