Curriculum Vitae
A summary of my education, experience, and activities.
Education
2020 - 2024
Ph.D. in Computer and Communication Sciences
EPFL (École Polytechnique Fédérale de Lausanne) · Lausanne, Switzerland
- Thesis: Technology Mapping and Optimization Algorithms for Logic Synthesis of Advanced Technologies
- Advisor: Prof. Dr. Giovanni De Micheli, Integrated Systems Laboratory (LSI)
2018 - 2020
M.Sc. in Computer Engineering
Télécom Paris, EURECOM · Biot, France
- Specialization in Smart Objects (joint master program with Politecnico di Torino)
- GPA 4.0/4
- Thesis: Implementation of Algorithms for Synthesis of Digital Circuits
2017 - 2020
M.Sc. in Computer Engineering
Politecnico di Torino · Torino, Italy
- Specialization in Embedded Systems (joint master program with Télécom Paris)
- Full marks with honor (110 cum laude / 110)
- Thesis: Implementation of Algorithms for Synthesis of Digital Circuits
2014 - 2017
B.Sc. in Computer Engineering
Politecnico di Torino · Torino, Italy
Experience
2024 - present
Senior R&D Staff Engineer
Synopsys Inc. · Sunnyvale, California, USA
- Research and development of synthesis algorithms for Fusion Compiler and Design Compiler
2020 - 2024
Doctoral Researcher
EPFL (École Polytechnique Fédérale de Lausanne) · Lausanne, Switzerland
- Integrated Systems Laboratory: electronic design automation (EDA), logic synthesis, and emerging technologies
- Teaching undergraduate and graduate courses and supervising Master's projects
- Advisor: Prof. Dr. Giovanni De Micheli
2022
Research Intern
X, the Moonshot Factory (Google X) · Mountain View, California, USA
- Logic synthesis and electronic design automation (EDA)
- Part of the work was published at DAC 2023
2020
R&D Engineer
Télécom Paris, EURECOM · Biot, France
- Implementation of a model-checker for embedded system models on TTool
- Work published at MODELSWARD 21, MODELSWARD 22, and in a Springer book chapter
- Best poster award at MODELSWARD 21
2019
Intern
Synopsys · Montbonnot-Saint-Martin, France
- Implementation of timing-driven algorithms for synthesis of digital circuits
2017 - 2024
Teaching Assistant
Politecnico di Torino & EPFL
- Politecnico di Torino: Algorithms and Programming in C, Object-Oriented Programming
- EPFL: Design Technologies for Integrated Systems, Real-Time Embedded Systems, Digital Systems Design
Projects
Mockturtle
A C++17 logic synthesis framework; development of logic synthesis algorithms.
TTool
A toolkit for edition, simulation and formal verification of UML and SysML diagrams; development of the SysML model-checker (AVATAR).
LDPC HW Decoder
Design of a Low Density Parity Check codes channel decoder for 5G wireless communications, with an efficient fixed-point FPGA implementation.
Skills
Programming
Domains
Languages
Service & Leadership
- Reviewer for TCAD, TODAES, ICCAD, DATE, DAC, IWLS, DDECS, and ISVLSI
- Core developer of Mockturtle, an open-source logic synthesis library
- Maintainer of the EPFL logic synthesis libraries (lstools-showcase) and contributor to the logic synthesis tool ABC
- Maintainer of the EPFL Combinational Benchmark Suite and its annual competition, with updates presented at the International Workshop on Logic & Synthesis (IWLS)