Talk, ICCAD 2023, San Francisco, California, USA
This presentation reviews methods to map circuits to multi-output cells and proposes a new scalable algorithm that increases the usage of multi-output cells during technology mapping improving by more than 5% the area over previous methods. The content of the presentation is available in the paper “Technology Mapping Using Multi-output Library Cells”.
Talk, DAC 2023, San Francisco, California, USA
This presentation proposes new methodologies for logic optimization and transistor-level synthesis using factored forms. The content of this presentation is available in the paper “Improving Standard Cell Design Flow using Factored Form Optimization”.
Talk, IWLS 2022,
This presentation proposes new methodologies for technology mapping on Adiabatic Quantum-Flux-Parametron Circuits. The content of this presentation is available in the paper “Depth-optimal Buffer and Splitter Insertion and Optimization in AQFP Circuits”.
Talk, IWLS 2021,
This presentation proposes to use a versatile mapping approach to optimize logic during logic synthesis. The content of this presentation is available in the papers “From logic to gates: A versatile mapping approach to restructure logic” and “A Versatile Mapping Approach for Technology Mapping and Graph Optimization”.