2024
Improving Delay-driven LUT Mapping with Boolean Decomposition
Efinix Inc. · Online
Talks
Invited, conference, and workshop presentations.
Invited Talks
2024
Improving Technology Mapping for Standard Cells
IBM Thomas J. Watson Research Center · Online
2024
EPFL Benchmark Results Update
International Workshop on Logic & Synthesis (IWLS) · Zurich, Switzerland
2024
The EPFL Logic Synthesis Libraries: Open-source Tools for Classical and Emerging Technologies
Free Silicon Conference (FSiC) · Paris, France
2024
Technology-aware Logic Synthesis for Superconducting Electronics
International Workshop on Quantum, Cryogenic and Superconductive Computing · Fukuoka, Japan
2023
EPFL Benchmark Results Update
International Workshop on Logic & Synthesis (IWLS) · Lausanne, Switzerland
2023
Improving Standard-Cell Design Flow using Factored Form Optimization
Cadence Design Systems Inc. · San Jose, CA, USA
2023
Technology Mapping Using Multi-output Library Cells
Google X · Online
2023
Improving Delay-driven LUT Mapping with Boolean Decomposition
AMD Inc. (Vivado team) · Online
2022
EPFL Benchmark Results Update
International Workshop on Logic & Synthesis (IWLS) · Online
2021
EPFL Benchmark Results Update
International Workshop on Logic & Synthesis (IWLS) · Online
Conference & Workshop Talks
2024
In Medio Stat Virtus: Combining Boolean and Pattern Matching
Asia and South Pacific Design Automation Conference (ASP-DAC) · Incheon, South Korea
2024
Algebraic and Boolean Methods for SFQ Superconducting Circuits
Asia and South Pacific Design Automation Conference (ASP-DAC) · Incheon, South Korea
2024
Scalable Logic Rewriting Using Don't Cares
Design, Automation & Test in Europe Conference (DATE) · Valencia, Spain
2024
Area-Oriented Resubstitution For Networks of Look-Up Tables
International Workshop on Logic & Synthesis (IWLS) · Zurich, Switzerland
2024
Practical Boolean Decomposition for Delay-driven LUT Mapping
International Workshop on Logic & Synthesis (IWLS) · Zurich, Switzerland
2023
Depth-optimal Buffer and Splitter Insertion and Optimization in AQFP Circuits
International Workshop on Logic & Synthesis (IWLS) · Online
2023
Depth-Optimal Buffer and Splitter Insertion and Optimization in AQFP Circuits
Asia and South Pacific Design Automation Conference (ASP-DAC) · Tokyo, Japan
2023
Technology Mapping Using Multi-output Library Cells
International Workshop on Logic & Synthesis (IWLS) · Lausanne, Switzerland
2023
Improving Standard-Cell Design Flow using Factored Form Optimization
Design Automation Conference (DAC) · San Francisco, CA, USA
2023
Technology Mapping Using Multi-output Library Cells
International Conference on Computer-Aided Design (ICCAD) · San Francisco, CA, USA
2022
A Versatile Mapping Approach for Technology Mapping and Graph Optimization
Asia and South Pacific Design Automation Conference (ASP-DAC) · Online
2021
From Logic to Gates: A Versatile Mapping Approach to Restructure Logic
International Workshop on Logic & Synthesis (IWLS) · Online