Technology Mapping and Optimization Algorithms for Logic Synthesis of Advanced Technologies
Published in PhD Thesis at EPFL, 2024
This thesis focuses on developing state-of-the-art logic synthesis methods for advanced technologies. These technologies include conventional CMOS for field-programmable gate arrays (FPGAs) and standard-cell-based designs, as well as superconducting electronics (SCE). In particular, we concentrate on the technology mapping problem, which involves translating a technology-independent circuit description into an interconnection of gates specific to a technology library.