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publications
Implementation of Algorithms for Synthesis of Digital Circuits
Published in Thesis at Politecnico di Torino and Telecom Paris, 2020
This thesis describes several techniques to be used in EDA synthesis tools to increase the QoR of digital circuits. We present circuit transformations able to improve the delay by pushing critical signals forward in the logic.
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Direct model-checking of SysML models
Published in 9th International Conference on Model-Driven Engineering and Software Development, 2021
Model-checking of high-level models, e.g. SysML models, usually first requires a model transformation to a low level formal specification. The present papers proposes a new model-checker that can be applied (almost) directly to the SysML model.
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From logic to gates: A versatile mapping approach to restructure logic
Published in International Workshop on Logic & Synthesis, 2021
This paper proposes a versatile mapping approach for restructuring logic that has two objectives: it can map from one technology-independent graph representation to another; it can map to a cell library.
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A Versatile Mapping Approach for Technology Mapping and Graph Optimization
Published in 27th Asia and South Pacific Design Automation Conference (ASP-DAC), 2022
This paper proposes a versatile mapping approach that has three objectives: it can map from one technology-independent graph representation to another; it can map to a cell library; it supports logic rewriting. The mapper is the first one of its kind to support remapping among various graph representations, thus enabling specialized mapping to emerging technologies and for security applications.
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SysML models verification relying on dependency graphs
Published in 10th International Conference on Model-Driven Engineering and Software Development, 2022
Incremental modeling of systems leads to the repeated verification of parts of systems models that were already verified in previous versions of the SysML model. This paper proposes to optimize the verification process by generating dependency graphs from SysML models.
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Majority-based design flow for AQFP superconducting family
Published in 2022 Design, Automation & Test in Europe Conference & Exhibition (DATE), 2022
Adiabatic superconducting devices are promising candidates to develop high-speed/low-power electronics. Being the technology fundamentally different from CMOS, new challenges are posed to design automation tools: library cells are controlled by multi-phase clocks, they implement the majority logic function, and they have limited fanout. We present a product-level RTL-to-GDSII flow for the design of Adiabatic Quantum-Flux-Parametron (AQFP) electronic circuits, with a focus on the special techniques used to comply with these challenges.
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The EPFL logic synthesis libraries
Published in arXiv preprint arXiv:1805.05121, 2022
We present a collection of modular open source C++ libraries for the development of logic synthesis applications. These libraries can be used to develop applications for the design of classical and emerging technologies, as well as for the implementation of quantum compilers.
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Utilizing XMG-based synthesis to preserve self-duality for RFET-based circuits
Published in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2022
Individual transistors based on emerging reconfigurable nanotechnologies exhibit electrical conduction for both types of charge carriers. These transistors, referred to as reconfigurable field-effect transistors (RFETs), enable dynamic reconfiguration to demonstrate either a p- or an n-type functionality. This duality of functionality at the transistor level is efficiently abstracted as a self-dual Boolean logic. In this article, we specifically aim to preserve self-duality by using Xor-majority graphs (XMGs) as the logic representation during logic synthesis and technology mapping.
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Dependency Graphs to Boost the Verification of SysML Models
Published in Springer, 2023
A drawback of this approach is that the entire SysML model is used for the verification, even if the property targets a sub-system of the model. In this paper, it is suggested to rely on dependency graphs to avoid applying model checking to the entire system when only a subset of the latter needs to be taken into account.
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Depth-optimal Buffer and Splitter Insertion and Optimization in AQFP Circuits
Published in 28th Asia and South Pacific Design Automation Conference (ASP-DAC), 2023
The Adiabatic Quantum-Flux Parametron (AQFP) is an energy-efficient superconducting logic family. AQFP technology requires buffer and splitting elements (B/S) to be inserted to satisfy path-balancing and fanout-branching constraints. In this work, we study the B/S insertion and optimization methods. In particular, the paper proposes: an algorithm for B/S insertion that guarantees global depth optimality; a new approach for B/S optimization based on minimum register retiming; a B/S optimization flow.
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Boolean Decomposition Revisited
Published in International Workshop on Logic & Synthesis, 2023
Ashenhurst-Curtis decomposition (ACD) is well-known and widely used in logic synthesis for logic restructuring to save area and reduce delay, and in technology dependent optimization to overcome structural bias when mapping into LUTs and LUT structures. However, available implementations of ACD suffer from excessive complexity and slow runtime. The paper offers several simplifications that allow for a fast and flexible implementation of ACD using truth tables for functions up to 16 inputs. A practical extension allows for an efficient use of ACD in delay-driven mapping, which can enhance state-of-the-art LUT mappers.
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Improving Standard-Cell Design Flow using Factored Form Optimization
Published in Design Automation Conference (DAC), 2023
Factored form is a multi-level representation of a Boolean function that readily maps into CMOS technology. In particular, the number of literals of a factored form correlates well with the number of transistors. This paper focuses on developing techniques for minimizing the total factored form literals count in an and-inverter graph.
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Synthesis of SFQ Circuits with Compound Gates
Published in Conference on Very Large Scale Integration (VLSI-SoC), 2023
Rapid single-flux quantum (RSFQ) is one of the most advanced superconducting technologies with the potential to supplement or replace conventional VLSI systems. However, scaling RSFQ systems up to VLSI complexity is challenging due to fundamental differences between RSFQ and CMOS technologies. Due to the pulse-based nature of the technology, RSFQ systems require gate-level pipelining. Moreover, logic gates have an extremely limited driving capacity. Path balancing and clock distribution constitute a major overhead, often doubling the size of circuits. Gate compounding is a novel technique that substantially enriches the functionality realizable within a single clock cycle. In this paper, we propose a technology mapping method for RSFQ circuits that exploits compound gates. Our results show, on average, a 33% lower logic depth with 24% smaller area, as compared to the state of the art.
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Technology Mapping Using Multi-output Library Cells
Published in International Conference on Computer-Aided Design (ICCAD), 2023
This paper presents a scalable method to increase the support of multi-output library cells in technology mapping. Our contributions include 1) an approach to detect multi-output cells, 2) a fast Boolean matching methodology, and 3) a technology mapping algorithm that supports multi-output cells. Unlike previous work, we address the mapping problem over the whole network. This has the advantage of optimizing area and delay without requiring many incremental steps.
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Algebraic and Boolean Methods for SFQ Superconducting Circuits
Published in Asia and South Pacific Design Automation Conference, 2024
Rapid single-flux quantum (RSFQ) is one of the most advanced and promising superconducting logic families, offering exceptional energy efficiency and speed. RSFQ technology requires delay registers (DFFs) and splitter cells to satisfy the path-balancing and driving-capacity constraints. In this paper, we present a comprehensive exploration of methods for synthesizing and optimizing SFQ circuits. In the experimental results, we show an average reduction in the area and delay of 43% and 34%, respectively, compared to the state-of-the-art.
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In Medio Stat Virtus: Combining Boolean and Pattern Matching
Published in Asia and South Pacific Design Automation Conference, 2024
Technology mapping transforms a technology-independent representation into a technology-dependent one given a library of cells. This process is performed by means of local replacements that are extracted by matching sections of the subject graph to library cells. Matching techniques are classified mainly into pattern and Boolean. These two techniques differ in quality and number of generated matches, scalability, and run time. This paper proposes hybrid matching, a new methodology that integrates both techniques in a technology mapping algorithm.
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Technology-Aware Logic Synthesis for Superconducting Electronics
Published in 2024 Design, Automation & Test in Europe Conference & Exhibition (DATE), 2024
Superconducting electronics provide us with cryogenic digital circuits that can rival established technologies in performance and energy consumption. This review focuses on methods, algorithms, and open-source design tools for logic synthesis of superconducting circuits in two major families: single-flux quantum (SFQ) circuits and adiabatic quantum flux parametron (AQFP).
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Scalable Logic Rewriting Using Don’t Cares
Published in 2024 Design, Automation & Test in Europe Conference & Exhibition (DATE), 2024
Logic rewriting is a powerful optimization technique that replaces small sections of a Boolean network with better implementations. In this paper, we propose a technique to enable the usage of don’t cares in logic rewriting based on pre-computed databases. We show how to process the database and perform Boolean matching with Boolean don’t cares, with negligible run time overhead.
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Late Breaking Results: Majority-Inverter Graph Minimization by Design Space Exploration
Published in IEEE/ACM Design Automation Conference (DAC), 2024
The majority-inverter graph (MIG) is a homogeneous logic network widely used in logic synthesis for majority-based emerging technologies. In this paper, we explore combinations of well-developed MIG optimization algorithms using an on-the-fly design space exploration strategy and present the latest best results on MIG size minimization of EPFL benchmarks.
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Technology Legalization and Optimization for Adiabatic Quantum-Flux Parametron
Published in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2024
Adiabatic quantum-flux parametron (AQFP) is an energy-efficient superconducting technology. Before physical design can be performed, AQFP technology mapping involves not only mapping logic into supported gate types but also legalizing the circuit to fulfill the technology-imposed constraints on path balancing and fanout branching by inserting buffer and splitter cells. In this paper, we (a) identify that the AQFP legalization problem is a scheduling problem; (b) propose linear-time depth-optimal scheduling and irredundant buffer insertion algorithms; (c) present heuristic optimization algorithms to further reduce buffer count; and (d) suggest an unsupervised design space exploration approach for AQFP technology mapping.
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Enhancing Delay-Driven LUT Mapping With Boolean Decomposition
Published in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2024
Ashenhurst-Curtis decomposition (ACD) is a decomposition technique used, in particular, to map combinational logic into lookup tables (LUTs) structures when synthesizing hardware designs. This paper presents a novel fast and versatile technique of ACD suitable for delay optimization. We use this new formulation to compute two-level decompositions into a variable number of LUTs and enhance delay-driven LUT mapping by performing ACD on the fly.
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Technology Mapping and Optimization Algorithms for Logic Synthesis of Advanced Technologies
Published in PhD Thesis at EPFL, 2024
This thesis focuses on developing state-of-the-art logic synthesis methods for advanced technologies. These technologies include conventional CMOS for field-programmable gate arrays (FPGAs) and standard-cell-based designs, as well as superconducting electronics (SCE). In particular, we concentrate on the technology mapping problem, which involves translating a technology-independent circuit description into an interconnection of gates specific to a technology library.
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talks
From Logic to Gates: A Versatile Mapping Approach to Restructure Logic
Published:
This presentation proposes to use a versatile mapping approach to optimize logic during logic synthesis. The content of this presentation is available in the papers “From logic to gates: A versatile mapping approach to restructure logic” and “A Versatile Mapping Approach for Technology Mapping and Graph Optimization”.
Depth-optimal Buffer and Splitter Insertion and Optimization in AQFP Circuits
Published:
This presentation proposes new methodologies for technology mapping on Adiabatic Quantum-Flux-Parametron Circuits. The content of this presentation is available in the paper “Depth-optimal Buffer and Splitter Insertion and Optimization in AQFP Circuits”.
Improving Standard Cell Design Flow using Factored Form Optimization
Published:
This presentation proposes new methodologies for logic optimization and transistor-level synthesis using factored forms. The content of this presentation is available in the paper “Improving Standard Cell Design Flow using Factored Form Optimization”.
Technology Mapping Using Multi-output Library Cells
Published:
This presentation reviews methods to map circuits to multi-output cells and proposes a new scalable algorithm that increases the usage of multi-output cells during technology mapping improving by more than 5% the area over previous methods. The content of the presentation is available in the paper “Technology Mapping Using Multi-output Library Cells”.
teaching
Teaching Assistant for Algorithms and Programming in C
Undergraduate course, Politecnico di Torino, 2017
Activities
Assisting students during the lab sessions to solve programming assignments.
Teaching Assistant for Object-Oriented Programming
Undergraduate course, Politecnico di Torino, 2018
Activities
Assisting students during the lab sessions to solve programming assignments.
Teaching Assistant for Real Time Embedded System
Graduate course, EPFL, 2021
Content
The course includes the study of models of management of an embedded system by polling, interruptions and using a real time kernel and these primitives of tasks management and synchronizations. Specialized programmable interfaces are carried out in VHDL to help with these measurements. A real time kernel is studied and used at the time of the laboratories. A system of acquisition is carried out and the gathered data transmitted by an embedded Web server. To ensure the real time acquisition and reading by the Web server, a multiprocessor system is developed and carried out on FPGA. An Accelerator makes it possible to facilitate the optimization of functions by hardware on FPGA. Cross development tools are used. Each topic is treated by a theoretical course and an associated laboratory. The laboratories are realized on a FPGA board especially developed for teaching. A real time operating system is studied and used with the laboratories.
Teaching Assistant for Design Technologies for Integrated Systems
Graduate course, EPFL, 2021
Content
The course will present the most outstanding features of hardware compilation, as well as the techniques for optimizing logic representations and networks. The course gives a novel, uptodate view of digital circuit design. Practical sessions will teach students the use of current design tools.
Teaching Assistant for Real Time Embedded System
Graduate course, EPFL, 2022
Content
The course includes the study of models of management of an embedded system by polling, interruptions and using a real time kernel and these primitives of tasks management and synchronizations. Specialized programmable interfaces are carried out in VHDL to help with these measurements. A real time kernel is studied and used at the time of the laboratories. A system of acquisition is carried out and the gathered data transmitted by an embedded Web server. To ensure the real time acquisition and reading by the Web server, a multiprocessor system is developed and carried out on FPGA. An Accelerator makes it possible to facilitate the optimization of functions by hardware on FPGA. Cross development tools are used. Each topic is treated by a theoretical course and an associated laboratory. The laboratories are realized on a FPGA board especially developed for teaching. A real time operating system is studied and used with the laboratories.
Teaching Assistant for Digital System Design
Undergraduate course, EPFL, 2023
Content
The course includes:
- abstractions in digital hardware systems, formalisms for system description
- Basics of digital design: Boolean algebra and representations, logic gates, combinational and sequential circuits, finite state machines
- Register-transfer-level (RTL) design: methodology translating a high-level (algorithmic) system description into control and datapath structures, foundations of synchronous digital design, timing and and timing constraints, basic architectural transformations, FPGA basics.
- VHDL: language basics and event-driven simulation, VHDL RTL design, synthesis and verification.
Teaching Assistant for Design Technologies for Integrated Systems
Graduate course, EPFL, 2023
Content
The course will present the most outstanding features of hardware compilation, as well as the techniques for optimizing logic representations and networks. The course gives a novel, uptodate view of digital circuit design. Practical sessions will teach students the use of current design tools.